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Hi,
In VHDL, you can define signals/variables using bit, bit_vector, std_logic & std_logic_vector. When you declare signals as bit/bit_vector, they can only take two values 0/1. When you use std_logic they can take 4 values 0/1/X/Z. When you only declare any signal / variable and do not initialize it , it does not have a value assigned to it and it defaults to X. So, after you declare a signal, you need to initialize it to a known value, either 0/1/Z.
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In Verilog 4-state types have 0/1/X/Z, but VHDL std_ulogic has 9 states (std_logic is just a resolved version of std_ulogic, allowing multiple drivers)
Also, in VHDL, all objects with no initial value default to their leftmost value, so for std_logic it is 'U', bit is '0', integer is -2^31 and so on.
IMO, std_ulogic is preferable to bit as it will allow you see various issues because of things being assigned to 'U', and you can also assign odd or illegal combinations to 'X' (Unknown) or '-' (dont care) and see these flow through in simulation.
By Default, Quartus (and most other compilers) will initialise registers to '0' where you have no initialisation. But memories will initialise to random noise when you havent set anything explicitly, so bare that in mind.
Honored Contributor
