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Hi,
In VHDL, you can define signals/variables using bit, bit_vector, std_logic & std_logic_vector. When you declare signals as bit/bit_vector, they can only take two values 0/1. When you use std_logic they can take 4 values 0/1/X/Z. When you only declare any signal / variable and do not initialize it , it does not have a value assigned to it and it defaults to X. So, after you declare a signal, you need to initialize it to a known value, either 0/1/Z.
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This post is missing some values. If you take a look in the ieee.std_logic_1164 library you can see:
type STD_ LOGIC is ( ‘U’, -- Uninitialized
‘X’, -- Forcing Unknown
‘0’, -- Forcing 0
‘1’, -- Forcing 1
‘Z’ -- High Impedance
‘W’, -- Weak Unknown
‘L’, -- Weak 0
‘H’, -- Weak 1
‘-’ -- don’t care
);
which give all the possible values. Using these will help you debug your design when simulating.
In simulation std_logic initialises to u and in synthisization it depends on the tool. If you really want a '0', then initialise it to '0'.
Honored Contributor
