Basic question about Signals

Hi,

In VHDL, you can define signals/variables using bit, bit_vector, std_logic & std_logic_vector. When you declare signals as bit/bit_vector, they can only take two values 0/1. When you use std_logic they can take 4 values 0/1/X/Z. When you only declare any signal / variable and do not initialize it , it does not have a value assigned to it and it defaults to X. So, after you declare a signal, you need to initialize it to a known value, either 0/1/Z.