Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

basic always block question

I have questions about always blocks. Both will use the following always block for context: 


always @ (posedge Clk)
begin
if (x1)
    q <= 1;
else if (x2)
    q <= 0;
else
    q <= q;
end

where q, x1 and x2 are all 1 bit wide.

Would this code 'prioritize' checking x1 before x2? What would happen if x1 and x2 were both high?

How exactly would it synthesize?

Also, if I want q to retain it's value, is it necessary for me to explicitly code that in the form of q <= q? or is there another way?

Thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    Would this code 'prioritize' checking x1 before x2?

    --- Quote End ---

    Obviously yes.

    --- Quote Start ---

    What would happen if x1 and x2 were both high?

    --- Quote End ---

    The same as only x1 high?

    --- Quote Start ---

    How exactly would it synthesize?

    --- Quote End ---

    Any logic fulfilling the behavioral description would be correct. In FPGA as D-FF with preceding logic. You can watch the synthesis result in Quartus post synthesis net list.

    --- Quote Start ---

    Also, if I want q to retain it's value, is it necessary for me to explicitly code that in the form of q <= q? or is there another way?

    --- Quote End ---

    The final else statement is redundant and can be omitted. A register keeps the previous state by default.