Honored ContributorHi,
Is there any function or backdoor access available to read/write the altsyncram memory model? I need to define some functions/tasks to read/write altsyncram mem model. One way is to define the tasks to drive the corresponding signals at it interface. I was wondering if any other way or some backdoor access is also available? I appriciate your help. Regards, skb
Honored ContributorYou can directly import / export memory contents in Modelsim with tcl commands.
Type "help mem save" "help mem load" in transcript console for further info. Update: don't think this will work from you HDL code though.Honored Contributorthe easiest way would be to write behavioural VHDL that Quartus infers memory from, with a custom built backdoor interface that that synthesisor ignores. It would be fairly simple to create in VHDL (and probably verilog too), but you need a good understanding of VHDL
Honored ContributorYou may also want to take a look at Modelsim's signal spy package, which allows your testbench to read and write signals in modules.
