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SKarp6's avatar
SKarp6
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5 years ago

AXI Translator from Platform Designer (QSYS) doesn't follow AXI4-Lite protocol spec.

Hello All, This might be a known problem. It looks like AXI Translator module has a bug. When you pick AXI4-Lite on master side AXI Translator expects that RID and BID signals will be set by a modul...
RichardT_altera's avatar
RichardT_altera
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5 years ago

I could not find any significant difference from the waveform diagram in modelsim. Perhaps you could help to share screenshot on it? Could you share both of your projects (hang and no hang) so I could duplicate the issue?

  • SKarp6's avatar
    SKarp6
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thanks a lot for reply.

    Here are waveforms I captured with SignalTap.

    Read transaction, no hang case, when translating to AXI4:

    Notice RID signal is set to ARID.

    Read transaction, hang case, when translating to AXI4-Lite:

    See RID remains zero. Both RID and BID are not connected inside of the translator when translating to AXI4-Lite.

    See axi4lite_quick_fix file with a hacky fix to my top of QSYS generated block. Unfortunately I cannot share whole design.

    To reproduce you need to run Platform Designer, instantiate HPS, then instantiate AXI translator, connect its slave side to AXI master on HPS and export master side as AXI4-Lite. You'll notice that RID and BID signals are not exported which is correct because AXI4-Lite doesn't use it, however AXI translator doesn't handle these signals correctly for HPS side. That's why it hangs when you try to access MMIO range.