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Altera_Forum's avatar
Altera_Forum
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17 years ago

Avolon-ST Packets generation error?

Hi

I am using Quartus 8.1. and I have a Nios connected to on-board FIFOs via two pipeline bridges. The FIFOs then connects via a Timing Adaptors to a custom components that simply maps the Avalon-ST signals to external signals.

The FIFOs have MM inputs and ST outputs.

Packet Support are enabled on all the components in the chain.

I get the following warnings: "Module dependency loop envolving:" (it then notes different combinations of my pipeline bridges and FIFOs).

I have generated this SOPC design and the code executes, but I never get any Start of Packet (SOP) and End of Packet (EOP) signals on the output FIFOs.

I opened the design in the RTL viewer and noticed that the generated code connects the SOP and EOP signals on the timing adaptors to GND. (See attached images) The input FIFOs seem to be correct.

Does anyone have any idea how to fix this? Is this a bug in SOPC or am I doing something wrong?

Any help will be appreciated.

Regards

Eric

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I guess everyone is on leave or this problem is to difficult for anyone to help with? ;-)

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I have received some feedback from Altera.

    There is a bug in the file at <Install Directory>/ip/altera/sopc_builder_ip/altera_avalon_fifo/em_fifo.pl in line 2823, where “Use_packet” should be “Use_Packet” (P must be capitalized).

    This seems to solve the problem.