Occasional ContributorAvalon MM Read of Custom module returns "deadc0de"
Hello,
I am having troubles diagnosing and solving this error. I mainly can't diagnose it because I don't know what is going on.
I have created some custom HDL using SystemVerilog that I have put into a module and turned into a Platform Designer IP (_hw.tcl). This module uses an Avalon Memory Mapped Interface. I have compiled the project with no errors and programmed the target FPGA. When I attempt to read from the module using system console, I get back the 32 bit hex word "deadc0de". I am not sure what is generating that word because my code doesn't implement that. All reads to the module (this includes the base address and offsets) returns "deadc0de".
I created two other modules with the same interface and they also have the same issue. I have other custom Platform Designer components using Avalon MM interfaces that were coded in VHDL by other people and they work.
What is returning "deadc0de"? Why is it returning "deadc0de"?
Thank you
I re-examined the Platform Design and I found the error. I had assumed the new modules were hooked up to System Console's Avalon port. They were not. "deadc0de" is the output from the default slave. I attempted a search of the code to find it originally, but it was hidden and I did not find it. Thank you for the direction.
