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Altera_Forum
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15 years ago

Avalon-MM pipeline bridge won't work with Stratix II devices

Hi all! I have a pretty simple system nios ii/f main_mem avalon_mm_pipeline_bridge timer_sys_clk sysid jtag_uart sgdma_tx sgdma_rx descriptor_memory tse_mac that run...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I could not find any explaination of my problem...

Addresses in system.h are correct (in avalon_mm_pipeline span).

Avalon-MM pipeline bridge is supposed to be transparent.

Software accesses a component described in system.h, CPU accesses the pipeline bridge, which relays the accesses to the corresponding component. Then the component 'answers' to the pipeline bridge that relays the answer to the CPU.

What I do not understand is that it works perfectly on the initial Stratix II GX project.