New Contributor
Super ContributorThis seems to be a bug to me. If standard had the interconnect, pro should have as well. Can you attached both of your design here in pro and std for me to investigate?
New ContributorWell I don't have a complete design in pro or standard (std isn't possible => stratix), but I attached an example in std, which I want to build in pro.
To clarify stuff again:
Std is at version 18.1, here the IP is visible and NOT labled internal in its tcl
Pro is at 19.4, IP invisible because its property is set to internal
The example I got the idea from was generated using pro 19.4, but is targeting an older version, so I guess the internal change occured in 19.X.
(the IP also got updated to version 19.1 guess here it was changed)
IP-Name: Avalon-MM Master Translator Intel FPGA IP (+ slave)
IP-Name (tcl): altera_merlin_master_translator_hw.tcl (+ slave)
IP-Path: .\Quartus\ip\altera\merlin\altera_merlin_master_translator (+ slave)
New in 19.?: set_module_property INTERNAL true
Attached a simple qsys std 18.1 dummy showing what I want to do, I would also be fine with other ways/IPs to archiv this.
I just found it charming how you managed to handle the various control busses from 12 transceivers in one bus.
Also attached: MAC/xcvr/10G example generated by quartus pro
For now, because the ip is still there after all, I just copied it from an other .qsys into my design.
