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Aswinkrishnan's avatar
Aswinkrishnan
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Avalon mm Master BFM

I have being trying to do bus simulation on my avalon slave with avalon mm master bfm. The simulation output is wrong. For example when I write to an address c0 and write data into it, but not writ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

I tested those statements without problem. There's no range of addresses being written. Attached two design files for your reference. First design file (avlmm_1x1_verilog.zip) translator result image:

Second design file (qwork.zip) perform single avalon write and single avalon read to pio control then compare the compatible of write and read data image:

Run the run_simulation.tcl. May be can try the testbench inside the files. In testbench, remember to define the correct parameters AV_ADDRESS_W, AV_SYMBOL_W and AV_NUMSYMBOLS.

Thanks,

Best regards,

Sheng

  • Aswinkrishnan's avatar
    Aswinkrishnan
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Thank you for the reply and I will look in to those files.

    I have an Avalon slave device with an 8-bit data width and multiple individually addressable 8-bit data registers with adjacent addresses. So, sometimes I want to write data to a single 8-bit data register in my address space. The BFM and/or the Avalon infrastructure are generating 4 successive addresses, not the single address I expect. It is as if the BFM and Avalon infrastructure are configured to do a 32-bit write, with 4 successive bytes of data.

    First, is it possible to do a single 8-bit write to my slave device?

    Secondly, if it is possible, what parameters should I set, and to what values, to achieve this?