Forum Discussion
Aswinkrishnan
Occasional Contributor
Occasional ContributorAvalon mm Master BFM
I have being trying to do bus simulation on my avalon slave with avalon mm master bfm.
The simulation output is wrong. For example when I write to an address c0 and write data into it, but not writ...
AswinkrishnanOccasional Contributor
Occasional ContributorI think there is a proper connection between master and the slave. I generated using the qsys. Can we check if it's proper in any other way?
I think I didn't assert waitrequest high but in the waveform, the mo_waitrequest is being asserted towards the end of it right? Is it because not asserting it high?
AswinkrishnanOccasional Contributor
Occasional ContributorIn qsys, for the avalon mm master bfm, I had enabled assert wait request high. I had checked it again.
