Forum Discussion
Altera_Forum
Honored Contributor
11 years agoHi, thank you - I solved my issue(s)! Finally, it seems that I had something wrong in my C code. I figured it out commenting out all C instructions and executing line by line, adjusted all type lengths cleanly, and figured out some related issue.
The hint with SignalTap was awesome, though. I read through ftp://ftp.altera.com/up/pub/altera_material/13.1/tutorials/verilog/signaltap.pdf (ftp://ftp.altera.com/up/pub/altera_material/13.1/tutorials/verilog/signaltap.pdf) for my Quartus II 13.1. Since I'm new to logic analyzers I still don't get quite, how the "triggers" actually work?! What is the difference between setting them on '1' or '0', or rising, falling, either rising and falling, or "don't care", respectively. Rarely I see really edges, but already seeing what is "set" and what not, helps me already. Currently I do single runs before, then execute the .c code, and do another single run. I don't see edges, but already helpful highs or lows. I really thought I'll need a special license for it, but it was just connecting the talk-back-feature in fact. For university purpose, just perfect! Great!!!