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Honored Contributor
Honored Contributoravalon fifo issue - module dependency loop
I have an Avalon ST-MM FIFO implemented in SOPC. After programming the FPGA, the first time I use NIOS to touch the FIFO CSR (init, clear, read, or whatever) the system hangs. If I then stop the NIOS...
Altera_ForumHonored Contributor
Honored ContributorHi all, I solved it by changing frequency in SDRAM controller. My Core(Cyclon IV) does not support the last frequency. Thanks for reading!
