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Altera_Forum's avatar
Altera_Forum
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16 years ago

Avalon bus - what makes it so special?

Hi,

i want to know the following information about Avalon bus

1. Architecture - is the bus architecture continuous or is the connection between maters and slaves dedicated.

2. If it is a dedicated bus connection then will the following modules be

present between each dedicated connection

a. Address Decoding

b. Data path multiplexing

c. Arbitration

d. Wait state instertion

3. Does this not mean the bus architecture shall take more logic resources?

4. What makes Avalon bus more special (apart from fact it comes with SOPC)?

5. When compared to AMBA bus can we say Avalon bus is more superior ?

6. What range of frequencies does the Avalon bus support?

7. How many gate count does the avalon bus take?

8. What are the common problems with Avalon bus

shall be greatly helpful if some one can clarify these queries

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    1. SOPC builder creates logic to connect specifically the master/slaves as described in the SOPC system. It's not a plug-and-play bus, if you add a component you need to regenerate all the bus logic. I guess it would be what you call 'dedicated'

    2. yes

    3. more than what?

    4. I wouldn't call it special. It is integrated with SOPC builder, and does its job very well

    5. superior in what? The question is too vague

    6. any one the hardware can support

    7. it depends

    8. I don't know any ;)
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    hi

    thanks for ur reply

    in short i want to compare the ABMA bus with Avalon bus in terms of:

    1. Consider a system which has Cortex M1 processor and few periherals

    What will be the difference performance-wise between AMBA and Avalon busses?

    a. Bus transaction type - Split or burst or any other

    b. Bus type - Shared or Dedicated

    c. Arbitration logic - centralized or de-centralised

    d. Bridges - any difference

    e. For Cortex m1 processor which is best bus - avalon / AMBA

    f. any other difference in this line...

    Thanks in advance
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Are the 'Avalon Bus' and 'Avalon Interconnect for Avalon MM components' essentially the same? I did not find any specification manual for the 'Avalon Bus' on the Altera website. The SOPC builder 'Help' also talks about 'Avalon Interconnect rather than the bus.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Avalon bus is designed for FPGAs. It's resource utilization adapts to the complexity of the configuration of your bus.

    As far as performance, fmax is usually determined by the components you've got connected and how. Latency can be extremely low (like 0) depending on the components in question.

    What you ought to do is compile a few simple systems and look at the resource utilization for yourself. Or just compile some of the reference designs and look at the resource utilization.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It is just a choice of words... when you design an SOPC system it is easier to see it as a bus, with all the masters and slaves connected to a same bus. But if you have a look at the RTL after compilation, SOPC builder in fact connects each slave to each master, meaning that it is fact an interconnecting architecture. You can even have two masters writing to two different slaves simultaneously, which would be impossible with a traditional bus.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thank you, Daixiwen. I am just getting acquainted with the Avalon Interconnect and it is indeed way cooler than traditional shared bus architectures.

    I, however, have trouble understanding arbitration. this (http://www.altera.com/literature/hb/qts/qts_qii54003.pdf) document talks about fairness based shares for each master with respect to a slave, which can be specified in the SOPC builder. What is a share? Is it a certain number of read/write bus cycles? Where can I read more about it? The document I have linked above and the avalon interface specifications manual are the only two documents I am referring to right now. Is there any other document where I can find more details on the Avalon Interconnect?

    Thanks.

    PPB
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    From the document:

    --- Quote Start ---

    One share represents permission to perform one transfer.

    --- Quote End ---

    Suppose two masters are connected to a slave. Master 1 has 5 shares on the slave and Master 2 has 1 share. This means that Master 1 is allowed to issue up to 5 consecutive transfers to the slave (read or write). If it only has 4 transfers it needs to make then it gives up it's 5th share to the other master (Master 2). Master 2 may then issue one transfer to the slave (read or write). After this, the arbiter goes back to Master 1 to see if it has any transfers to make. If so, Master 1 is again allowed to make up to 5 transfers.

    With regards to bursts; if a master is a burst master, the document specifies:

    --- Quote Start ---

    For burst masters, the size of the burst determines the number of cycles that the master has access to the slave, and the selected arbitration shares have no effect.

    --- Quote End ---

    Or essentially, a burst master really only gets one share on the slave and it uses its burst value to control how many accesses it will make.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thank you Jake. I think I get it. I'm trying to figure out how this would relate to my design.