Avalon bus - what makes it so special?

Thank you, Daixiwen. I am just getting acquainted with the Avalon Interconnect and it is indeed way cooler than traditional shared bus architectures.

I, however, have trouble understanding arbitration. this (http://www.altera.com/literature/hb/qts/qts_qii54003.pdf) document talks about fairness based shares for each master with respect to a slave, which can be specified in the SOPC builder. What is a share? Is it a certain number of read/write bus cycles? Where can I read more about it? The document I have linked above and the avalon interface specifications manual are the only two documents I am referring to right now. Is there any other document where I can find more details on the Avalon Interconnect?

Thanks.

PPB