Avalon BFM - Test Program

Hi Dave,

thanks again for your very good answer! This helps alot.

I found the BFMs and will try them as soon as possible. I already saw that you used avalon read/write signals as active high, whereas I use them active low. But since this is VHDL, I have no problems tweaking them to my needs. . . .

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It depends what features of the Altera API you want. Personally Avalon-MM read/write burst/single was enough for my needs.

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The feature I need is that I'm able to simulate my Qsys system just the way it behaves like if it is connected to the HPS of a Cyclone V device.

Right now, my main problem is the adressing of registers inside my components.

If I want to address subsequent registers of my components from the HPS, I have to increment the HPS address by 4. Additionally, I have implemented an Avalom MM Master in my Qsys system that runs "free", say without any connection to the HPS and reads data out of avalon MM slaves of my custom components in order to serialize them and stream them via the DMA of the HPS to the Linux system on the HPS. Anyway, this master component also has to increase the addresses by 4 if it wants to read subsequent data words out of my components.

Right now, I simulate my data transfers with hand written testbenches that lack the interconnet logic of the Avalon bus. In my testbenches I have to increment the address by 1 if I would like to read subsequent data from my components. So I have to "adjust" something in my test models in order to simulate. But if I do this, I do not test the system anymore that will finally run in the finished design.

What I also think is a neat feature of the BFMs is that it is integrated in Qsys. All interconnect logic between the Avalon bus and my component would be done by qsys instead of me "wiring" all those signals together.

From the first glance at your BFMs I cannot tell, if they fit my above mentioned requirements/wishes. Maybe you can answer that in a sentence, or two.

Regards,

Maik