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This brings me to the third point: My VHDL problem. Unfortunately, I did not find your "avalon_bfm_pkg.vhd" file that I'm really keen on to look into! It seems not to be contained in any of the links you provided. I also looked a little bit around your Website but had no luck there, too (besides finding other interesting stuff . . . ).
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Oops, the last link above should have been to the code zip file, not the slides ...
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104code_hawkins.zip --- Quote Start ---
I really would go with your Verilog testbench that stimulates the avalon mm master bfm and I would adjust that to my component, but since I use Modelsim ASE, I have no chance to use mixed language simulation.
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Ok.
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In the latest Quartus version (14) there seems to be full VHDL support for the Avalon (and AXI) BFMs. Is there any chance that one (maybe you?!? ;-) ) could take the qsys_system of your tutorial, generates it with VHDL simulation model and builds a little VHDL BFM testbench that feeds the Qsys generated simulation model with some stimulus like you did it with your verilog testbench?
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That is my plan, when I update the tutorial, but I've been too busy :)
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I tried to analyze your verilog code in order to understand how you used the BFM API. I found out that you have this "object" .BFM, on which you call `BFM.init();. I really have no idea what I have to do to implement something similar in a VHDL testbench.
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This is where the difference in Verilog and VHDL shows. In Verilog you can "reach down into" the design using a hierarchical path. You can now do this in VHDL-2008, but I haven't tried using it. The "proper" way to do this in VHDL is to use a BFM I/O object (created using a record and a resolution function). Altera have chosen to go the "hacked" route for their VHDL BFM support in that they have defined a global signal within a package and then provide their BFM functions with a BFM master index ... in my opinion an ugly solution.
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The next thing is how you use those "avalon_write()" and "avalon_read()" functions. How do I implement those calls in VHDL.
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Use the VHDL BFM I wrote, it should be good enough to test your own custom VHDL components,
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Next thing is that I don't know if theis $display() command is something verilog specific, or if it is command that modelsim uses.
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Its a Verilog task provided by the simulator. Look at my VHDL testbench and you'll find a log_pkg.vhd with logging functions.
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What kind of packages or libraries do I have to import in a VHDL testbench so that I can achive the same resutls with your verilog testbench.
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The DSP code uses VHDL, so look at its testbenches. I wrote a really basic Modelsim testbench in a couple of other threads too ...
http://www.alteraforum.com/forum/showthread.php?t=45770 http://www.alteraforum.com/forum/showthread.php?t=32386 These don't include the BFM, but they have examples of the logging procedures.
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Your qsys_system_dut port definition does only contain ports of the components for the components that are under test (like the LED PIO and the Buttzon PIO), but none for the master BFM. How do the BFM API calls "know" what their destination is?
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Read the source code. `BFM is defined at the top of the testbench as the path to the BFM component. When the testbench code calls `BFM.<some function>, the function definition is inside the BFM Verilog that was added into the Qsys system.
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What I additionally would like to mention is that I of course looked at the VHDL example used in the "Avalon Verification IP Suite" user guide. I have to say that these files " test_program_pkg.vhd" and "test_program.vhd" totally overwhelmed me. I just don't know where to find the essential stuff that I basically need and from what I can start to extend the testbench accoring to my needs.
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Take a look at my simplified code, and if you don't like it, and pester me enough, I'll take a look at Altera's VHDL support to see if its worth using.
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Maybe you can give me some hints, or provide the full link to your VHDL testbench if this answers a lot of my questions, already.
One thing about this VHDL testbench: You wrote that you "wrote your own BFM". So that means that it is not based on the Avalon Verification IP API, right? Because using this API would be my final goal for testing of my design.
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It depends what features of the Altera API you want. Personally Avalon-MM read/write burst/single was enough for my needs.
Cheers,
Dave
Honored Contributor
