Avalon BFM - Test Program

Hi again,

I was able to combine your tutorial qsys_system (compiled as VHDL simulation model) with the above mentioned "test_program_pkg.vhd" and "test_program.vhd" and an additional tb.vhd file also derived from the "Avalon Verification IP Suite" user guide tutorial.

It all compiled in modelsim and when I run the simulation, at least, the clock is ticking :-) . . . . . This is easy to understand (also for me) because the clock is generated in the tb.vhd file that has the qsys_system instantiated it as component and (via portmapping) provided this clock to the component.

Now, I wanted to use the test_program.vhd to provide some stimulus to the master bfm. But I fear that something is missing in order to connect the test_program.vhd with the qsys_system.vhd.

I uploaded my project that is based on your tutorial as zip file. I added the above mentioned testbench files. Maybe somebody has an idea how I can get this running to get nearly the same results like I get if I run the verilog simulation provided by Dave.

Thanks,

Maik