Avalon BFM - Test Program

Hi Dave,

firstly, pretty interesting stuff that you are working on. I think I can use some of this DSP information, too, in my future work. Thanks for providing this!

Second, I succesfully simulated your LED/Button PIO Design using the verilog approach according to your tutorial. This is EXACTLY what I would like to implement for my own design.

This brings me to the third point: My VHDL problem. Unfortunately, I did not find your "avalon_bfm_pkg.vhd" file that I'm really keen on to look into! It seems not to be contained in any of the links you provided. I also looked a little bit around your Website but had no luck there, too (besides finding other interesting stuff . . . ).

I really would go with your Verilog testbench that stimulates the avalon mm master bfm and I would adjust that to my component, but since I use Modelsim ASE, I have no chance to use mixed language simulation.

In the latest Quartus version (14) there seems to be full VHDL support for the Avalon (and AXI) BFMs. Is there any chance that one (maybe you?!? ;-) ) could take the qsys_system of your tutorial, generates it with VHDL simulation model and builds a little VHDL BFM testbench that feeds the Qsys generated simulation model with some stimulus like you did it with your verilog testbench?

I tried to analyze your verilog code in order to understand how you used the BFM API. I found out that you have this "object" .BFM, on which you call `BFM.init();. I really have no idea what I have to do to implement something similar in a VHDL testbench.

The next thing is how you use those "avalon_write()" and "avalon_read()" functions. How do I implement those calls in VHDL.

Next thing is that I don't know if theis $display() command is something verilog specific, or if it is command that modelsim uses.

What kind of packages or libraries do I have to import in a VHDL testbench so that I can achive the same resutls with your verilog testbench.

Your qsys_system_dut port definition does only contain ports of the components for the components that are under test (like the LED PIO and the Buttzon PIO), but none for the master BFM. How do the BFM API calls "know" what their destination is?

etc.etc.

@edit: What I additionally would like to mention is that I of course looked at the VHDL example used in the "Avalon Verification IP Suite" user guide. I have to say that these files " test_program_pkg.vhd" and "test_program.vhd" totally overwhelmed me. I just don't know where to find the essential stuff that I basically need and from what I can start to extend the testbench accoring to my needs.

Maybe you can give me some hints, or provide the full link to your VHDL testbench if this answers a lot of my questions, already.

One thing about this VHDL testbench: You wrote that you "wrote your own BFM". So that means that it is not based on the Avalon Verification IP API, right? Because using this API would be my final goal for testing of my design.

Thanks again for your kind help!

Regards,

Maik