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Okay, I couldn't resist an read the Qsys part of your tutorial pdf.
It looks quit good. Very nice writing an the steps are very clear.
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Thanks!
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However, i did not found a hint to the API calls to control the BFMs. But maybe I have to check the source code of the testbench which I really will do tomorrow.
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Yeah, the testbench code is pretty self-explanatory. The hard part was figuring out which SystemVerilog BFM routines needed to be called. The qsys_vip.zip has a working example, so ultimately you don't really care, you can just copy the read/write tasks (just copy the whole testbench and edit it).
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Any chance to make your tutorials also for VHDL?
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The Verification suite did not used to have VHDL models, so I wrote my own BFM with limited Avalon-MM transaction support, so that I could test VHDL-only designs in Modelsim-ASE (single-language mode). Take a look at the code for this presentation ...
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-111paper_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-111slides_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-111slides_hawkins.zip
ESC-104Code_Hawkins\dsp_tutorial\vhdl\lib\packages\test\avalon_bfm_pkg.vhd
and then look at the VHDL testbench for the tutorial. Its a simple BFM relative to what the Verification IP Suite provides, but its good enough :)
Cheers,
Dave
Honored Contributor
