Automatic use of internal block RAMs

Using a shared variable implies write-before-read behaviour. Historically Altera could only infer read-before-write behaviour and if you needed write-before-read it had to be done using an altsyncram with the appropriate generic.

It now appears that write-before-read can be infered, but using a variable in a single process, rather than a shared variable over 2 processes.

To be safe, Both Xilinx and Altera will always infer a ram using a signal rather than shared variable.