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PElm
New Contributor
New ContributorAutomatic use of internal block RAMs
I'm translating code from Xilinx devices to Intel to see if we could switch to Altera FPGAs. Xilinx tools automatically translate VHDL memory operations to block-ram without need to use macros or co...
Tricky
Occasional Contributor
Occasional ContributorUsing a shared variable implies write-before-read behaviour. Historically Altera could only infer read-before-write behaviour and if you needed write-before-read it had to be done using an altsyncram with the appropriate generic.
It now appears that write-before-read can be infered, but using a variable in a single process, rather than a shared variable over 2 processes.
To be safe, Both Xilinx and Altera will always infer a ram using a signal rather than shared variable.
