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Altera_Forum's avatar
Altera_Forum
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17 years ago

automatic firmware revision for VHDL

Dear Experts, i'd like to introduce to my design one register containing a firmware revision. Very probably the firmware revision would be a data when the VHDL code was checked out from the CV...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi All,

thanks for useful info. In fact I did something similar because I didn't know about PRE_FLOW_SCRIPT_FILE feature of quartus. I have built a small TCL script which generates entity having one output vector of 32 bits, which is fed by output of 'clock seconds' TCL command. However in order to run compilation I have used TCL script which does it for me, and not the PRE_FLOW_SCRIPT_FILE. Your solution is better because it keeps the current development flow intact.

d.