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Altera_Forum
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12 years ago

Auto RAM Block Balancing Failure

Hi All, I have an interesting situation that I am unable to explain and is causing me some grief. The design targets the Stratix 3 family and instantiates many large memories using an in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

A follow-up:

I still have no optimal solution, so if anybody has info, I would still be happy to hear it.

However, I do have a more tolerable workaround. If a memory with ADDR_SIZE>14 is specified, the module instantiates an array of memories with ADDR_SIZE=14 and adds extra address decoding and output selecting logic. In this case, Quartus balances the block types properly even though the total number of bits instantiated is the same as before.