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HenryMittel's avatar
HenryMittel
Icon for New Contributor rankNew Contributor
4 years ago
Solved

auto-generated file "is missing"

I created a copy of a working design (because I need to move to the newer Arria 10 family), modified the Qsys (because it uses hard-IP that is different for the new family), adapted the wrapper for t...
  • HenryMittel's avatar
    HenryMittel
    4 years ago

    Hello sstrell,

    Thank you for explaining the difference between including .qsys and .qip in the settings file. I thought the "IP Regeneration Policy" under "IP Settings" in Assignments | Settings would decide about that.

    While your answer wasn't directly helpful, it prompted me to take an Nth look at the IP Settings page ... and give "Verilog" instead of "VHDL" another try. I also turned off the regeneration and manually regenerated (as Verilog) the system in the Qsys designer. Now, the errors with the auto-generated files are gone - and I can start working on the errors I introduced.

    And yes, I am still using the old Quartus 15.0 - because I was told that my RapidIO license, whose maintenance expired in 2015, can only be used with Quartus 15 or earlier. Should I question that advice?

    Thanks for the assistance with the original problem.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

I'm presuming you are using the Standard edition of Quartus.

Which Qsys (now called Platform Designer) file have you added to your Quartus project: .qsys or .qip?

If you want the system to get automatically (re)generated every time you compile your Quartus project, add the .qsys file to your project.

If you want to manually generate your system every time you make a change, do that in Qsys (Platform Designer) and then add the generated .qip file to your Quartus project.

This error sounds like an issue with the system not getting auto regenerated, so try manually regenerating in Qsys (Platform Designer) and adding the .qip to your project. The strings you mention are randomly generated and get listed in the .qip file, so perhaps Quartus is not seeing the updated file names because of an old .qip.

HenryMittel's avatar
HenryMittel
Icon for New Contributor rankNew Contributor
4 years ago

Hello sstrell,

Thank you for explaining the difference between including .qsys and .qip in the settings file. I thought the "IP Regeneration Policy" under "IP Settings" in Assignments | Settings would decide about that.

While your answer wasn't directly helpful, it prompted me to take an Nth look at the IP Settings page ... and give "Verilog" instead of "VHDL" another try. I also turned off the regeneration and manually regenerated (as Verilog) the system in the Qsys designer. Now, the errors with the auto-generated files are gone - and I can start working on the errors I introduced.

And yes, I am still using the old Quartus 15.0 - because I was told that my RapidIO license, whose maintenance expired in 2015, can only be used with Quartus 15 or earlier. Should I question that advice?

Thanks for the assistance with the original problem.