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Honored Contributor
Honored Contributorauto gated clock conversion help
I am trying to implement some ASIC code in an FPGA, and unfortunately the code has gated clocks. Because of the huge clock skew problems this causes I was hoping to use the Auto Gated Clock Conversio...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Thanks for your help and advice, Rysc. Does anyone out there know if there are any tricks to using the Auto Gated Clock Conversion option? Any help would be appreciated. Thanks! --- Quote End --- Hi, the Quartus "gate clock conversion" will only work if there are only, and, or, xor gates in the control of the clock gating. Maybe your Latch is the problem. Try to describe your gating only with gates. What kind of clock gating are you doing? Are the clocks only switched off in order to save power or do you clock dividing ? Has every clock gating cell different control signals or are there groups which uses the same signals ? If yes, you can at least reduce the number of gating cells. Kind regards GPK
