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Altera_Forum
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16 years ago

auto gated clock conversion help

I am trying to implement some ASIC code in an FPGA, and unfortunately the code has gated clocks. Because of the huge clock skew problems this causes I was hoping to use the Auto Gated Clock Conversio...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Thanks for your help and advice, Rysc.

Does anyone out there know if there are any tricks to using the Auto Gated Clock Conversion option? Any help would be appreciated. Thanks!

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Hi, Did you get any solution for this issue? I'm facing the same problem in my design.

Thanks,

Gopal