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Altera_Forum's avatar
Altera_Forum
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16 years ago

auto gated clock conversion help

I am trying to implement some ASIC code in an FPGA, and unfortunately the code has gated clocks. Because of the huge clock skew problems this causes I was hoping to use the Auto Gated Clock Conversio...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Yep, my solutions are useless for you. (There are not enough altclkctrl blocks). I would take a small subsection of real code(at least that has real clock enables) and file an SR on it, so an Altera engineer can look at it and hopefully direct to what's wrong.