Audio Codec

Hi all,

I have a question regarding the audio codec inside the DE2 board. I'm trying to DE2 board audio codec as my AD/DA convertor for audio signals.

Apparently, altera has this as lab 12 in the following link,

altera.com/education/univ/materials/digital_logic/labs/unv-labs.html

I'm trying to understand this part of the lab,

The first element of the buffer is always visible on the readdata left and

readdata right outputs when the read ready signal is asserted. The next element can be read by asserting the

read signal, which ejects the current sample and a new one appears one or more clock cycles later, if read ready

signal is asserted.

Here is what I came up with. I have confusion on what I'm suppose to the with the code to get it to work, anybody has any ideas on this?

Also, it seems like the process and the if statement doesn't work in this code since the library was not included and after I added the library I got some other errors, I don't think this is suppose to be solved with process and if statements.

/////////////////////////////////

// Your code goes here

process (CLOCK_50, read_ready,read, write_ready,write)

begin

if rising_edge(CLOCK_50) then

if(read_ready='1' and read='1') then

readdata_left <= writedata_left;

readdata_right <= writedata_right;

end if;

if(write_ready='1' and write='1') then

writedata_left <= readedata_left;

writedata_right <= readdata_right;

end if;

end if;

end process;

/////////////////////////////////

assign writedata_left = ;

assign writedata_right = ;

assign read = ...;

assign write = ...;