Asynchronous Ripple-Counter without compiler warning?

Afaik, there are very few warnings in quartus you can really suppress. These usually come about because you're doing something that an FPGA isnt really designed for,

Btw, code appraisal: you shouldnt really read inout ports. The "prefered" method is to declare q_out an out and have an internal local signal.

Or switch on the VHDL 2008 compile compatability and you can read out ports (like in verilog), to avoid using inout.