Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Asynchronous pulse generator code rising edge

Newbie here. I need to generate pulses at rising/falling edges of an input signal. I would like to avoid using an internal clock for this application because parts of my system is inherently as...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

So you are suggesting that I use the enable option for all flip-flops and counters, and enable with the function I am currently wrestling with? I can use the square wave (my input signal) to make a single count? I have no problem with that, but, as an amateur, I do not see how that will provide different results in practice (though I can see how I could use that to make synchronized pulses, which is why I have considered implementing something like this). Is this more reliable? Does this have something to do with the architecture of FPGA's and/or CPLD's? Thanks again.