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Altera_Forum
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9 years ago

Asynchronous pulse generator code rising edge

Newbie here. I need to generate pulses at rising/falling edges of an input signal. I would like to avoid using an internal clock for this application because parts of my system is inherently as...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Simulating in Quartus II, the outputs begin high and stay high. Also, I can't say I whether I need to synthesize or not. Honestly, I usually just make a block diagram, hit the compiler button, and program the FPGA or CPLD. My applications have been simple and it seems to have worked for me thus far.

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