Asynchronous load

readEN is a signal that will be unrelated to clock meaning that I'll be asserting readEN via some switch or something.

validin is an external signal generated by another board so I definitely think it would need to be registered too.

So I went ahead and added these two lines right under the elsif(clk'event and clk='1'):

		validinreg <= validin;
		readENreg <= readEN;

It's basically correct to register unrelated signals this way. Using a single register stage actually still keeps a finite risk of metastable events, so two cascaded registers are usually suggested. The likelihood of metastability is however low and the effect doesn't show up in simulation, so it's definitely not related to the presently observed problems.

Apart from adding the registers which I've done, how do you go about troubleshooting a design that, as soon as you add output signals so you have a clue of whats going on, starts to work?

Two points.

Not all of the internal signals are there though. Many of them aren't in fact.

I think the best thing to do is start from scratch with a good design plan and do this correctly. You guys have been really helpful so far and I really appreciate it. Perhaps you can let me know if I'm on the right track?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity fixer is
	port
	(
		clk,reset : in std_logic;
		input: in std_logic_vector(3 downto 0); -- the input ethernet frame
		validin: in std_logic; --the valid signal that we get
		readEN: in std_logic; --high when we want to read from memory	
		validout: out std_logic; --high when we're sending a valid frame out
		output : out std_logic_vector(3 downto 0) --output has value if we're reading
	);
end fixer;
architecture structure of fixer is
	--registering inputs
	signal reg_validin : std_logic;
	signal reg_input : std_logic_vector(3 downto 0);
	signal reg_readEN : std_logic;
	--------------------------------
	signal wren : std_logic; -- memory write enable
	signal load: std_logic; -- load enable for the 24 bit shift registers
	signal stop: std_logic; -- tells memory not to read and the 1 bit shift registers not to change their value
	signal sfd: std_logic_vector(7 downto 0); -- parallel output of 4 - 2 bit shift registers
	signal qin : std_logic_vector (3 downto 0); --input to memory
	signal send: std_logic_vector(3 downto 0); --output of shift set of shift registers, to memory unless we're loading our end of frame delimiter
	signal hold1: std_logic_vector (3 downto 0); --output of memory
	signal hold2: std_logic_vector (3 downto 0); --output of 4 - 2 bit shift registers and input to 4 - 24 bit shift registers
	signal address: std_logic_vector(14 downto 0);--address to read and write from memory at
	signal outload0: std_logic_vector(23 downto 0); --vectors to load into the 24 bit shift registers
	signal outload1: std_logic_vector(23 downto 0);
	signal outload2: std_logic_vector(23 downto 0);
	signal outload3: std_logic_vector(23 downto 0);
	
		
	component shiftreg2 is
	PORT
	(
		clock		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		shiftout		: OUT STD_LOGIC 
	);
	end component;
	
	component framestore is
	port
	(
		clk,reset : in std_logic;
		input: in std_logic_vector(3 downto 0); -- the input ethernet frame
		address: in std_logic_vector(14 downto 0);
		valid: in std_logic; --valid signal that comes with input
		readEN: in std_logic; --high when we want to read from memory
		output : out std_logic_vector(3 downto 0) --output, has value if we're reading
	);
	end component;
	
	component shiftreg1 IS
	PORT
	(
		clock		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
		shiftout		: OUT STD_LOGIC 
	);
	END component;
	
	component shiftreg24 is
	PORT
	(
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
		load		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		shiftout		: OUT STD_LOGIC 
	);
	end component;
		
begin	
	
	process(clk,reset)
	begin
	if(reset = '1') then
		wren <= '0';
	    load <= '0';
		stop <= '0';
		address <= "000000000000000";
		outload0 <= "000000000000000000000000";
		outload1 <= "000000000000000000000000";
		outload2 <= "000000000000000000000000";
		outload3 <= "000000000000000000000000";
	elsif(clk'event and clk = '1') then	 
	--register inputs
	reg_input <= input;
	reg_validin <= validin;
	reg_readEN <= readEN;
	
	--figuring out address
	
	--writing to memory
	
	--reading from memory
	
	end if;
	end process;
	
	--input to memory
	bit3in: shiftreg port map(clk,reset,input(3),sfd(7 downto 6),send(3));
	bit2in: shiftreg port map(clk,reset,input(2),sfd(5 downto 4),send(2));
	bit1in: shiftreg port map(clk,reset,input(1),sfd(3 downto 2),send(1));
	bit0in: shiftreg port map(clk,reset,input(0),sfd(1 downto 0),send(0));
	--memory
	mem: framestore port map(clk,reset,qin,address,wren,readEN and not stop,hold1);
	--output of memory
	bit3hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(3),hold2(3));
	bit2hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(2),hold2(2));
	bit1hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(1),hold2(1));
	bit0hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(0),hold2(0));
	--24 bit shift registers
	bit3out: shiftreg24 port map(clk,outload3,load,reset,hold2(3),output(3));
	bit2out: shiftreg24 port map(clk,outload2,load,reset,hold2(2),output(2));
	bit1out: shiftreg24 port map(clk,outload1,load,reset,hold2(1),output(1));
	bit0out: shiftreg24 port map(clk,outload0,load,reset,hold2(0),output(0));
	
end structure;