Asynchronous load

It should be executed exactly once on the first read, but for some reason, on some versions of the hardware that I simulate it on in quartus it does not execute at all!

The said problem doesn't occur with your previous posted switch20base version. Inserting the above code, it behaves strange, but the code doesn't seem meaningful, you're repeating the same if condition twice.

That's strange...maybe try with this. This is the exact code I have now and it's behaving exactly as I said. What behavior are you seeeing? What condition is being repeated twice?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity fixer is
	port
	(
		clk,reset : in std_logic;
		input: in std_logic_vector(3 downto 0); -- the input ethernet frame
		validin: in std_logic; --the valid signal that we get
		
		--loadout : out std_logic;
		--holdout : out std_logic_vector(3 downto 0);
		addressout : out std_logic_vector(14 downto 0);
		--countout: out integer range 0 to 25;
		wrenout: out std_logic;
		
		readEN: in std_logic; --high when we want to read from memory
		validout: out std_logic; --high when we're sending a valid frame out
		output : out std_logic_vector(3 downto 0) --output has value if we're reading
	);
end fixer;
architecture structure of fixer is
	signal address: std_logic_vector(14 downto 0);
	signal wren : std_logic;
	signal load: std_logic;
	signal stop: std_logic;
	signal temp: std_logic_vector (11 downto 0);
	signal qin : std_logic_vector (3 downto 0);
	signal send: std_logic_vector(3 downto 0);
	signal hold1: std_logic_vector (3 downto 0);
	signal hold2: std_logic_vector (3 downto 0);
	signal sfd: std_logic_vector(7 downto 0);
	signal expect_sfd: std_logic;
	signal expect_efd: std_logic;
	signal first_read: std_logic;
	signal just_now: std_logic;
	signal sfd_counter: integer range 0 to 25;
	signal efd_counter: integer range 0 to 25;
	signal efd_counter2: integer range 0 to 25;
	signal valid_counter: integer range 0 to 9;
	signal outload0: std_logic_vector(23 downto 0);
	signal outload1: std_logic_vector(23 downto 0);
	signal outload2: std_logic_vector(23 downto 0);
	signal outload3: std_logic_vector(23 downto 0);
	signal check0: std_logic_vector(23 downto 0);
	signal check1: std_logic_vector(23 downto 0);
	signal check2: std_logic_vector(23 downto 0);
	signal check3: std_logic_vector(23 downto 0);
	
	
	component framestore is
	port
	(
		clk,reset : in std_logic;
		input: in std_logic_vector(3 downto 0); -- the input ethernet frame
		address: in std_logic_vector(14 downto 0);
		valid: in std_logic; --valid signal that comes with input
		readEN: in std_logic; --high when we want to read from memory
		output : out std_logic_vector(3 downto 0) --output, has value if we're reading
	);
	end component;
	
	component shiftreg is
	PORT
	(
		clock		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		shiftout		: OUT STD_LOGIC 
	);
	end component;
	
	component shiftreg1 IS
	PORT
	(
		clock		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		shiftout		: OUT STD_LOGIC 
	);
	END component;
	
	component shiftreg24 is
	PORT
	(
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
		load		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
		shiftout		: OUT STD_LOGIC 
	);
	end component;
		
begin	
	
	process(clk,reset,validin,readEN,load,address,wren,first_read)
	begin
	if(reset = '1') then
		sfd_counter <= 0;
		efd_counter <= 0;
		efd_counter2 <= 0;
		valid_counter <= 0;
		validout <= '0';
		stop <= '0';
		expect_sfd <= '1';
		expect_efd <= '0';
		first_read <= '1';
		just_now <= '0';
		address <= "000000000000000";
		outload0 <= "000000000000000000000000";
		outload1 <= "000000000000000000000000";
		outload2 <= "000000000000000000000000";
		outload3 <= "000000000000000000000000";
	elsif(clk'event and clk = '1') then	 
		--writing
		if(validin = '1' and expect_sfd = '1' and sfd(7 downto 0) = "11001110") then
			expect_sfd <= '0';
			wren <= '1';
		elsif(validin = '0' and sfd_counter < 25 and (not expect_sfd = '1') and readEN = '0') then
			wren <= '1';
			expect_efd <= '1';
			sfd_counter <= sfd_counter + 1;
		elsif(sfd_counter = 25 and readEN = '0') then
			wren <= '0';
			sfd_counter <= 0;
			expect_sfd <= '1';
			expect_efd <= '0';
		elsif(validin = '1' and expect_efd = '1' and sfd_counter < 25) then
			sfd_counter <= sfd_counter + 1;
		end if;
		
		if(readEN = '1' and first_read = '1') then
			first_read <= '0';
			address <= "000000000000000";
		elsif((wren = '1' or readEN = '1') and stop = '0' and just_now = '1') then
				address <= address - "11";
				just_now <= '0';
		elsif(wren = '1' or (readEN = '1' and stop = '0' and just_now = '0')) then
				address <= address + '1';
		end if;
		
		load <= '0';
		
		--reading
		if(readEN = '1' and efd_counter = 24 and expect_sfd = '1') then
			stop <= '1';
			just_now <= '1';
			efd_counter <= 0;
			validout <= '0';
		elsif(readEN = '1' and hold1 = "1011" and expect_sfd = '1') then
			expect_sfd <= '0';
			expect_efd <= '1';
			load <= '1';
			outload3 <= "111111111111111100000000";
			outload2 <= "000000000000000000000000";
			outload1 <= "111111111111111100000000";
			outload0 <= "100000000000000000000000";
		    valid_counter <= valid_counter + 1;
		elsif(readEN = '1' and expect_sfd = '1' and stop = '1' and efd_counter2 < 23) then
			efd_counter2 <= efd_counter2 + 1;
			validout <= '0';
		elsif(readEN = '1' and expect_sfd = '1' and stop = '1' and efd_counter2 = 23) then
			stop <= '0';
			efd_counter2 <= 0;
		elsif(readEN = '1' and hold1 = "1111" and expect_efd = '1' and efd_counter < 23) then
			efd_counter <= efd_counter + 1;
		elsif(readEN = '1' and efd_counter = 23 and expect_efd = '1') then
			expect_efd <= '0';
			expect_sfd <= '1';
			efd_counter <= efd_counter + 1;
			load <= '1';
			outload0 <= "000000000000000000000000";
			outload1 <= "000000000000000000000000";
			outload2 <= "000000000000000000000000";
			outload3 <= "000000000000000000000000";
		elsif(readEN = '1' and not(hold1 = "1111")) then
			efd_counter <= 0;
		end if;
		
		if(valid_counter < 9 and valid_counter > 0) then
			valid_counter <= valid_counter + 1;
		elsif(valid_counter = 9) then
			validout <= '1';
			valid_counter <= 0;
		end if;
	end if;
	end process;
	
	--input to memory
	bit3in: shiftreg port map(clk,reset,qin(3),sfd(7 downto 6),send(3));
	bit2in: shiftreg port map(clk,reset,qin(2),sfd(5 downto 4),send(2));
	bit1in: shiftreg port map(clk,reset,qin(1),sfd(3 downto 2),send(1));
	bit0in: shiftreg port map(clk,reset,qin(0),sfd(1 downto 0),send(0));
	--memory
	mem: framestore port map(clk,reset,send,address,wren,readEN and not stop,hold1);
	bit3hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(3),hold2(3));
	bit2hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(2),hold2(2));
	bit1hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(1),hold2(1));
	bit0hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(0),hold2(0));
	bit3out: shiftreg24 port map(clk,outload3,load,reset,hold2(3),check3,output(3));
	bit2out: shiftreg24 port map(clk,outload2,load,reset,hold2(2),check2,output(2));
	bit1out: shiftreg24 port map(clk,outload1,load,reset,hold2(1),check1,output(1));
	bit0out: shiftreg24 port map(clk,outload0,load,reset,hold2(0),check0,output(0));
	
	--input
	qin <= "1111" when validin = '0' and sfd_counter < 25 and (not expect_sfd = '1') else input;
	--output
	
	--temp
	--loadout <= load;
	--holdout <= hold1;
	--countout <= efd_counter;
	addressout <= address;
	--wrenout <= wren;
		
end structure;

O.K. I see now, that the problem is apparently caused by an insufficient setup time for read_en. This clarifies, why you get different results with different chip families and speed grades. Changing read_en assertion to clk rising edge make the address counter operate correctly.

I'm sorry, but I don't really understand what you mean. All of my code takes place under the if statement involving clk'event and clock = 1. Isn't that a rising edge? What would I be doing differently?

One thing to note, the board we use in lab has the Cyclone II EP2C35F672C6N chip on it. This chip isn't in the quartus simulator. The closest I can find is the EP2C35F672C6 which it does work on in the simulator. It also works on the EP2C35F672C7 but not the EP2C35F672C8. Do you think that means it will definitely work on the board I have in the lab?

It's definitely a really really small timing issue. I ran the simulation with the EP2C35F672C8 device and everything was a cycle too late but when I added in some output signals so I could see where the problem was, everything worked fine. How do you troubleshoot an issue that goes away whenever you try and observe it? Heisenberg Uncertainty Principle of VHDL...

Here's my most recent version:

The timing analysis doesn't show errors with your code. But this only means, that the internal timing is correct. The problem is however with the external signals, e.g. read_en. You assert read_en at the falling_edge of clk. This 5 ns setup time relative to clk input is apparently not sufficient under all conditions.