This is a shift register question that I'm looking to get some light shed on. I have a 4 16bit shift registers that I'm using to detect a pattern. I feed bits into the shift regs until they match a pattern, at which point I replace the entire contents of the 4 shift registers with something else in a parallel load. The problem is that on one cycle, the pattern is detected and on the next clock cycle, the parallel load occurs. But also occurring on this cycle is the normal serial load. So the parallel load and the serial load collide and the parallel load seems to win and the 4 bits that I wanted to be shifted in serially are lost. Is it possible to do the comparison and load on the same cycle so that the first set of 4 bits on the serial input don't get lost? Is there a special shift register setting for this? There's a setting for asynchronous load in lpm_shiftreg but its greyed out Thanks

Naturally you can't put two drives on same registers at same clk. I am not clear what you want to achieve but in general stream processing if I want to detect a pattern I use pipeline(equivalent to shift) then detect and take action. For example if I want to detect the pattern "F2FC012A" then want to replace data with "AB" at that point I can do this: --in a clked process: data_1d <= data_in; data_2d <= data_1d; data_3d <= data_2d; if data_pipe = x"F2FC012A" then data_out <= x"AB"; else data_out <= data_3d; -- or any other stage end if; -- outside clked process: data_pipe <= data_in & data_1d & data_2d & data_3d;

In my opinion, it's no good idea to use an asynchronous load. Use a synchronous load in the next cycle instead, shifting the replacement data by one position, concatenated with the new serial input.

I ended up solving the problem by using a single DFF. Once I do the parallel load, I pass the data through the DFF so it doesn't get stomped on, and then through the shift register

What's a good way to do a large comparison and large parallel load? Basically I have my sram connected to a 4 wide DFF, connected to 4 24 bit wide shift registers. When I see the pattern "1011" in the DFF, I need to load data into the 4 24 bit wide shift registers. I also need the ability to check whether the data in the 24 bit registers is equal to some 96 bit value. I notice that after the first if statement is hit, (the "1011" pattern is detected and a parallel load is completed), on the next cycle the second if statement gets triggered even though the data in the shift registers is not equivalent. I'm sure it has to do with how I'm doing my comparison and parallel loading. Is there a better way to do it then this? Here's some lines from my code: --reading if(readEN = '1' and hold1 = "1011" and expect_sfd) then expect_sfd <= FALSE; expect_efd <= TRUE; load <= '1'; outload <= "111111111111111100000000000000000000000000000000111111111111111100000000100000000000000000000000"; validout <= '1'; elsif(readEN = '1' and check = "1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111" and expect_efd) then expect_efd <= FALSE; expect_sfd <= TRUE; load <= '1'; outload <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; validout <= '0'; stop <= '1'; end if; end if; end process; --memory mem: framestore port map(clk,reset,send,wren,readEN and not stop,hold1); bit3hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(3),smallsfd(3 downto 3),hold2(3)); bit2hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(2),smallsfd(2 downto 2),hold2(2)); bit1hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(1),smallsfd(1 downto 1),hold2(1)); bit0hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(0),smallsfd(0 downto 0),hold2(0)); bit3out: shiftreg24 port map(clk,outload(95 downto 72),load,reset,hold2(3),check(95 downto 72),output(3)); bit2out: shiftreg24 port map(clk,outload(71 downto 48),load,reset,hold2(2),check(71 downto 48),output(2)); bit1out: shiftreg24 port map(clk,outload(47 downto 24),load,reset,hold2(1),check(47 downto 24),output(1)); bit0out: shiftreg24 port map(clk,outload(23 downto 0),load,reset,hold2(0),check(23 downto 0),output(0));

I'm not really motivated to guess about the missing parts of code fragments. There are also many possible misunderstandings about what you regarded as incorrect design behaviour. As I already suggested in another thread: Providing a Quartus archive of an example design and a test waveform would help a lot.

Asynchronous load | Altera Community

36 Replies

Altera_Forum
Honored Contributor
16 years ago
I didn't really think about it. Now that I think about it, the only way I can forsee this possibly working is if the source of the data (an ethernet PHY board) runs at the same clock speed as the FPGA. How else would this be able to work correctly then? I'd still need to register the inputs though right? Just because they're running at the same speed, the clocks could be not completely in sync with each other right?
Altera_Forum
Honored Contributor
16 years ago
The PHY board transmits at 25 MHz and the FPGA runs at 50 MHz. So does that mean that for the simulation to be accurate, I should run the simulation clock at 50 MHz and provide a new set of 4 bits every 2 FPGA cycles?
Altera_Forum
Honored Contributor
16 years ago
Or I can just create a clock divider and not worry about that!
Altera_Forum
Honored Contributor
16 years ago
Wow it works so much better now! I can change to a different device/add or remove output ports and it all still works. The code didn't even really change that much except for the clock divider and registering those inputs.

Something else I thought of, when I actually hook this up to hardware I'm going to have to 25 MHz clocks (one from the phy board, one from the fpga). The code I wrote relies on the fact that they are at the same speed so that the data I'm supplying is in line with the data I'm receiving. Could I use a FIFO as a buffer for the data and just pump it in at one clock speed (the phy board clock speed) and read it at another speed ( the fpga clock speed) and then as long as the fifo is long enough, I shouldn't have to worry about the clocks violating some setup time?
Altera_Forum
Honored Contributor
16 years ago
Yes a FIFO is one of the usual means to move data between unsynchronized clock domains. The Quartus FIFO MegaFunction has all options to handle this situation. Actually, the FIFO depth requirement isn't high, because Ethernet has a clock accuracy specification of +/- 100 ppm, so the required buffer elasticity isn't more than a few bytes, even with extra large frames.
Altera_Forum
Honored Contributor
16 years ago
That's good to know. I've been messing around with the fifo buffer and the one thing I'm confused about is how the read and write request signals. I assume that I want to be reading and writing all the time. But if one clock is faster than the other (say my fpga clock is faster) then it will read the same value again if the buffer is empty. I've been messing around with this by using a 30mhz clock and a 25 mhz clock which is a huge stretch and I can see that if I just read and write all the time I'll run into problems.

Forum Discussion

Asynchronous load

36 Replies

Recent Discussions

USB-BlasterII mounts as "USB-Blaster variant"

Quartus Dark Theme on Linux - Solution

Error(23098) when using IPM_IOPLL on Agliex 7

Quartus 13.1 License

Highlight similar instances of a selected word fails when scrolling