Asynchronous load

Naturally you can't put two drives on same registers at same clk.

In my opinion, it's no good idea to use an asynchronous load. Use a synchronous load in the next cycle instead, shifting the replacement data by one position, concatenated with the new serial input.

I ended up solving the problem by using a single DFF. Once I do the parallel load, I pass the data through the DFF so it doesn't get stomped on, and then through the shift register

What's a good way to do a large comparison and large parallel load? Basically I have my sram connected to a 4 wide DFF, connected to 4 24 bit wide shift registers. When I see the pattern "1011" in the DFF, I need to load data into the 4 24 bit wide shift registers. I also need the ability to check whether the data in the 24 bit registers is equal to some 96 bit value.

		--reading
		if(readEN = '1' and hold1 = "1011" and expect_sfd) then
			expect_sfd <= FALSE;
			expect_efd <= TRUE;
			load <= '1';
			outload <= "111111111111111100000000000000000000000000000000111111111111111100000000100000000000000000000000";
		    validout <= '1';
		elsif(readEN = '1' and check = "1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111" and expect_efd) then
			expect_efd <= FALSE;
			expect_sfd <= TRUE;
			load <= '1';
			outload <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
			validout <= '0';
			stop <= '1';
		end if;
	end if;
	end process;
	
	--memory
	mem: framestore port map(clk,reset,send,wren,readEN and not stop,hold1);
	bit3hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(3),smallsfd(3 downto 3),hold2(3));
	bit2hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(2),smallsfd(2 downto 2),hold2(2));
	bit1hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(1),smallsfd(1 downto 1),hold2(1));
	bit0hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(0),smallsfd(0 downto 0),hold2(0));
	bit3out: shiftreg24 port map(clk,outload(95 downto 72),load,reset,hold2(3),check(95 downto 72),output(3));
	bit2out: shiftreg24 port map(clk,outload(71 downto 48),load,reset,hold2(2),check(71 downto 48),output(2));
	bit1out: shiftreg24 port map(clk,outload(47 downto 24),load,reset,hold2(1),check(47 downto 24),output(1));
	bit0out: shiftreg24 port map(clk,outload(23 downto 0),load,reset,hold2(0),check(23 downto 0),output(0));

I'm not really motivated to guess about the missing parts of code fragments. There are also many possible misunderstandings about what you regarded as incorrect design behaviour. As I already suggested in another thread: Providing a Quartus archive of an example design and a test waveform would help a lot.

I can do that. It's a lot of code to look through though.

Thanks, I'll look into it tomorrow. Can you tell which signal in the simulation output is correct in the first case and wrong in the second? At which time exactly?

Not sure exactly what you mean but, if you run the simulation you can see that when readEN goes high there are two good places to look and thats where loadout goes high because that's when I'm doing the big parallel loads. The first one is ok (the first loadout = high) but the second one is not ok. I think the reason it's not ok is that it takes about 3 cycles to get something read out of memory and so if I write my code not taking this into account, I lose some values somewhere. It's just getting so bloated and complicated that its hard to figure out what to do.

I managed to make some progress. It does correctly complete the simulation however, when I change the device from the Stratix II to some of the Cyclone chips, it no longer works. I understand that the hardware is different but I don't understand how the same code will work differently.

I've traced the problem to this code in the process block:

		if(readEN = '1' and first_read = '1') then
			address <= "000000000000000";
			first_read <= '0';
		elsif((wren = '1' or readEN = '1') and stop = '0') then
				address <= address - "11";
				just_now <= '0';
		elsif((wren = '1' or readEN = '1') and stop = '0') then
				address <= address + '1';
		end if;