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Altera_Forum's avatar
Altera_Forum
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16 years ago

Asynchronous load

This is a shift register question that I'm looking to get some light shed on. I have a 4 16bit shift registers that I'm using to detect a pattern. I feed bits into the shift regs until they match a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I can do that. It's a lot of code to look through though.

Here's the link:

http://tinyurl.com/ycjlqyx (http://tinyurl.com/ycjlqyx)

The VHDL file in question is fixer.vhd

The test waveform to use is newtest1.vwf.

If you compile and run the wave form you can see I'm basically trying to write some ethernet frames to memory and then read them out. When I read them out I'm trying to generate a full preamble to prepend to the start of frame delimiter. Also when I read an "end of frame delimiter" (in this case 12 bytes of all 1's) I replace the "end of frame delimiter" with all 0's. There are two ethernet frames that I try and write and then read in this waveform. You can see how when they are being read, I correctly generate the first ethernet frames, preamble, retrieve the data, and replace the end part, but then for some reason the first few pieces from the next frame don't get read, among other problems.