Asynchronous load

What's a good way to do a large comparison and large parallel load? Basically I have my sram connected to a 4 wide DFF, connected to 4 24 bit wide shift registers. When I see the pattern "1011" in the DFF, I need to load data into the 4 24 bit wide shift registers. I also need the ability to check whether the data in the 24 bit registers is equal to some 96 bit value.

I notice that after the first if statement is hit, (the "1011" pattern is detected and a parallel load is completed), on the next cycle the second if statement gets triggered even though the data in the shift registers is not equivalent. I'm sure it has to do with how I'm doing my comparison and parallel loading. Is there a better way to do it then this?

Here's some lines from my code:

		--reading
		if(readEN = '1' and hold1 = "1011" and expect_sfd) then
			expect_sfd <= FALSE;
			expect_efd <= TRUE;
			load <= '1';
			outload <= "111111111111111100000000000000000000000000000000111111111111111100000000100000000000000000000000";
		    validout <= '1';
		elsif(readEN = '1' and check = "1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111" and expect_efd) then
			expect_efd <= FALSE;
			expect_sfd <= TRUE;
			load <= '1';
			outload <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
			validout <= '0';
			stop <= '1';
		end if;
	end if;
	end process;
	
	--memory
	mem: framestore port map(clk,reset,send,wren,readEN and not stop,hold1);
	bit3hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(3),smallsfd(3 downto 3),hold2(3));
	bit2hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(2),smallsfd(2 downto 2),hold2(2));
	bit1hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(1),smallsfd(1 downto 1),hold2(1));
	bit0hold: shiftreg1 port map(clk,readEN and not stop,reset,hold1(0),smallsfd(0 downto 0),hold2(0));
	bit3out: shiftreg24 port map(clk,outload(95 downto 72),load,reset,hold2(3),check(95 downto 72),output(3));
	bit2out: shiftreg24 port map(clk,outload(71 downto 48),load,reset,hold2(2),check(71 downto 48),output(2));
	bit1out: shiftreg24 port map(clk,outload(47 downto 24),load,reset,hold2(1),check(47 downto 24),output(1));
	bit0out: shiftreg24 port map(clk,outload(23 downto 0),load,reset,hold2(0),check(23 downto 0),output(0));