Async FIFO to solve tricky issue with a funky input clock?

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Could you sample the data on both edges of the 10MHz clock - so effectively a 20MHz sample rate. Then synchronise both bits to one edge of the 10Mhz clock?

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Interesting idea. I'll consider this.

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This sounds more like a digital signal processing application, than a clock-domain crossing problem.

Does your analog circuit really generate edges, or is it really level transitions (high for some time, and then low again)?

Perhaps you can come up with a digital filtering scheme that is effectively a low-pass filter / averaging circuit that gives you the power-estimate you're interested in.

Could you provide more details on the analog circuit and perhaps a block diagram and example of the digital waveform input to the FPGA?

Cheers,

Dave

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The input clock I'm looking at is the output of a comparator. A voltage is applied across a capacitor then a oneshot is used to discharge it. This creates a current that is compared in the comparator to a known level. I think this is how it works but I'm not an analog guy so I'm a little hazy on the details. I did get a guarantee that they can promise me at least 30ns of high time and 30ns of low time so there shouldn't be any min/max time violations in the gates. Although I can fit anything onto an FPGA, this will end up on an ASIC with severe gate resitrictions so a big digital circuit isn't really an option. I'm trying to limit this to less than 25 flops.

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I would implement the following pieces to process this.

1. Somehow I need to transfer pulse information to synchronous domain right? So a safe way is to count in asyn domain with a counter in the asynchronous clock domain, convert its output to gray counter. In synchronous clock comain all you do is to keep your system counter and apply received pulse counts.

async counter-> bin2gray -> clock domain crossing->gray2bin -> interpret counter changes.

Let's say you implemented a 4 bit counter in async domain.

Let's say asynchronous counter is doing the following.

1 2 3 4 .... 14 15 0 1

Remember in the sync domain all you do is to calculate increments and apply to your FSM counter.

So your sync logic which receives counts, will convert them to +0 to +7 increment values. (I assume async clock is no more than 7 times faster than sync clock)

When you decide to count down, all you need to do is to subtract new counts coming in.

Good luck.

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I like this idea a lot actually. This is essentially what I was thinking of doing with an async fifo but I couldn't quite formulate what the hacks to get it to work are. Really I'm just utilizing gray code more so than the async FIFO. I think this may work.