Async FIFO to solve tricky issue with a funky input clock?

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I'm not sure if this is the right section because this is my first time posting here so correct me if I'm wrong.

here is the design problem:

I need to count the number of positive edges on the asynchronous clock. If this number goes above a certain threshold (let's say, 25 edges), I need to send a signal to FSM in the system clock domain that I've reached my limit. Now I also need to decrement this count at fixed intervals (let's say, minus 1 every 500us). This issue then becomes I'm decrementing the count with the system clock but incrementing it with the async clock.

Thanks

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I would implement the following pieces to process this.

1. Somehow I need to transfer pulse information to synchronous domain right? So a safe way is to count in asyn domain with a counter in the asynchronous clock domain, convert its output to gray counter. In synchronous clock comain all you do is to keep your system counter and apply received pulse counts.

async counter-> bin2gray -> clock domain crossing->gray2bin -> interpret counter changes.

Let's say you implemented a 4 bit counter in async domain.

Let's say asynchronous counter is doing the following.

1 2 3 4 .... 14 15 0 1

Remember in the sync domain all you do is to calculate increments and apply to your FSM counter.

So your sync logic which receives counts, will convert them to +0 to +7 increment values. (I assume async clock is no more than 7 times faster than sync clock)

When you decide to count down, all you need to do is to subtract new counts coming in.

Good luck.