Async FIFO to solve tricky issue with a funky input clock?

--- Quote Start ---

Each positive edge represents a packet of power that has gone through the analog circuit

--- Quote End ---

This sounds more like a digital signal processing application, than a clock-domain crossing problem.

Does your analog circuit really generate edges, or is it really level transitions (high for some time, and then low again)?

Perhaps you can come up with a digital filtering scheme that is effectively a low-pass filter / averaging circuit that gives you the power-estimate you're interested in.

Could you provide more details on the analog circuit and perhaps a block diagram and example of the digital waveform input to the FPGA?

Cheers,

Dave