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Altera_Forum's avatar
Altera_Forum
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11 years ago

Async FIFO to solve tricky issue with a funky input clock?

I came up with a solution, thanks everyone.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Could you sample the data on both edges of the 10MHz clock - so effectively a 20MHz sample rate. Then synchronise both bits to one edge of the 10Mhz clock?