Async FIFO to solve tricky issue with a funky input clock?

if your your input signal (clock) changes frequency or is off but without glitches then you can just count up on it (count1)

Once you reach threshold then generate flag for that in this clock domain.

The system clock can read this flag directly and there is no need for two stage synchroniser since flag is going to be sampled soon again and again while it stays at same level.

you then count down on system clock(count2).

As such I don't see any problem.

If your input clock has glitches it then can't be used as clock.