Async FIFO to solve tricky issue with a funky input clock?

--- Quote Start ---

It sounds to me like you could have a counter clocked by your asynchronous clock along with a combinatorial comparison for the limit. The limit output would then go through a synchronizer to the FSM clock domain. Similarly, your decrement flag would come from the FSM domain and then be synchronized in the async clock domain. That means the decrement would be delayed by two async clock edges, but that should be fine.

Create a simulation using Modelsim. That way you can try with two fixed frequency clocks, eg., 1MHz and 5MHz, and then once you have the logic working, you can try a variable clock signal in the asynchronous domain and see that it really works just like a fixed clock. The main thing is that in real hardware, you'll want to make sure your async clock does not have runt high or low times, but it sounds like you've already got that under control.

Cheers,

Dave

--- Quote End ---

This is ideal but unfortunately the async domain will eventually stop oscillating (0MHz). I can't synchronize the decrement signal to it because it may never get a clock again. When you go above the threshold, you do something in the FSM that has some feedback to the async domain. What that ends up doing is causing the async clock to slow down until it eventually shuts off. That means the decrement may be high but it might never get clocked in. Does that make sense?

Thanks.