assigning pins location to a component pin

Hi Dave

I'll take you up on your offer :), please see this simple top level entity:

--- Quote Start ---

package tcl_test is

type HW is (dff_board, srff_board);

end tcl_test;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY work;

USE work.tcl_test.all;

ENTITY simple IS

GENERIC (board: HW);

PORT

(

--for dff board

D : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

CLK : IN STD_LOGIC;

ENA : IN STD_LOGIC;

Q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

-- for srff board

S : IN STD_LOGIC;

CLK2 : IN STD_LOGIC;

R : IN STD_LOGIC;

Q3 : OUT STD_LOGIC

);

END simple;

ARCHITECTURE bdf_type OF simple IS

-- for dff board

COMPONENT my_dffe

GENERIC

(

BUS_WIDTH : INTEGER

);

PORT

(

D : IN STD_LOGIC_VECTOR(BUS_WIDTH - 1 DOWNTO 0);

CLK : IN STD_LOGIC;

ENA : IN STD_LOGIC:= '1';

Q : OUT STD_LOGIC_VECTOR(BUS_WIDTH - 1 DOWNTO 0)

);

END COMPONENT;

-- for srff board

COMPONENT my_srffe

PORT(S : IN STD_LOGIC;

CLK : IN STD_LOGIC;

R : IN STD_LOGIC;

Q : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

tagDFF: IF (board= dff_board) GENERATE

b2v_inst : my_dffe

GENERIC MAP

(

BUS_WIDTH => 2

)

PORT MAP(D => D,

CLK => CLK,

ENA => ENA,

Q => Q);

END GENERATE;

tagDFF: IF (board= srff_board) GENERATE

b2v_inst1 : my_srffe

PORT MAP(S => S,

CLK => CLK2,

R => R);

Q => Q3);

END GENERATE;

END bdf_type;

--- Quote End ---

as you can see in this simple project there are 2 kinds of board: one for DFF and the other for SRFF. the board type is defined by an external tcl script.

please show me how to write tcl that declares only the pins (and components) related to the current hardware.

thanks in advance

Ron

P.S

i'll try to get a hold on one of Brent Welch's books so I can study more on my own