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Altera_Forum's avatar
Altera_Forum
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8 years ago

assign two clocks

Hi,

I have a design with two clocks.

The first one (named "clk") is correctly assigned in my sdc file with: 

create_clock -name "clk" -period 5.000ns

but my second clock (named "clock2") is generating a warning. I've tried to add: 

create_clock -name "clock2" -period 40.000ns

but I still have a warning. "clock2" is not a port, it's generated from "clk". How should I assign that?

Thank you.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    I don't use a PLL or input/output pins as it's a simple internal clock divider. I really don't know how to resolve these warnings.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    I don't use a PLL or input/output pins as it's a simple internal clock divider. I really don't know how to resolve these warnings.

    --- Quote End ---

    The simplest and least problem clock divider is a PLL. A logic based clock divider can cause lots of timing problems as you can get a lot of skew on it. A PLL is almost always the simplest and best solution (not least as the constraints come for free with the derrive_pll_clocks SDC command)