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Honored Contributor
Honored Contributorassign two clocks
Hi, I have a design with two clocks. The first one (named "clk") is correctly assigned in my sdc file with: create_clock -name "clk" -period 5.000ns but my second clock (named "clock2")...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I don't use a PLL or input/output pins as it's a simple internal clock divider. I really don't know how to resolve these warnings. --- Quote End --- The simplest and least problem clock divider is a PLL. A logic based clock divider can cause lots of timing problems as you can get a lot of skew on it. A PLL is almost always the simplest and best solution (not least as the constraints come for free with the derrive_pll_clocks SDC command)
