Assign SDC files on each VHDL component project

As long as your source synchronous interface is inside the FPGA, and is described as such in your HDL code then there is no need to constrain it, it will be handled automatically by Quartus. You only need to constrain the input/output interfaces.

False paths and multicycles shouldn't depend on the inputs, but on the way your components are internally designed. Usually false paths are necessary when you transfer signals from one clock domain to another, and multicycles if you have a long combinatorial block that you know will take several cycles to complete, and have designed your component in accordance. Those are specific cases, and if you don't think you need them, then you probably don't ;)