Assign SDC files on each VHDL component project

I think what rochmadp is asking is: is there a way to automatically incorporate .sdc files from a lower level in the top level?

Some of the module ones designs have to do with specific hardware and is often re-used in other projects. E.g. a high-speed LVDS parallel bus input (as from ADCs, CMOS sensors, ...) is a low level module which you ideally design at its smallest, just the physical pins and some internal ports. To see whether the module will fly you actually have to constrain the inputs, hence you write a small .sdc file. But later on when you include the lower level module in the top design one has to manually (a lot of copy/paste) re-create the SDC constraints. Of-course the Altera Gurus do this all with Tcl-scripts (and Perl, and ...).

An interim solution is to write the lowest level test module .sdc in 2 pieces. One that constrains the internal ports and a second, to be included by the first one, that constrains the physical pins. The higher level .sdc sets a few variables for the second one to use. This way the second .sdc is a bit easier to re-use in a top-level project as one only has to update the variable names.