Arria V Transceiver Clocking

Indeed, the Custom PHY IP only offers CMU as for transceiver channel PLL (in Qts II 13.1.0 for the time being).

Keep in mind a channel PLL can be configured either as a CMU PLL for the TX PMA or a CDR to clock the RX PMA.

For Duplex operation, the channel PLL is necessary configured as a CDR. Therefore, the channel PLL is no longer available as a CMU PLL to clock the TX PMA. The only remaining TX PLL source is a fPLL (or an ATX PLL if you can afford Arria V GZ devices…). As fPLL frequency can be set up to 1.6GHz, this limits the data rate up to 3.2Gbps (the channel PLL VCO operates at half the data rate and serializer/deserializer are likely working on rising and falling edges of the VCO clock i.e., in DDR mode).

While the Custom PHY IP doesn’t offer any input for an external TX PLL source, the Native PHY does !

It is named “ext_pll_clk” (Tick “Use external TX PLL” in the TX PMA section of the Native PHY IP Core). Simply feed this input with a fPLL which frequency is set to half the TX data rate (remember: Max. frequency is 1.6GHz).

Channel bonding is another issue but using separate clock sources for your RX path and TX path should provide you enough flexibility to reach a proper instantiation scheme and get the fitter successfull.

Oliver